[PATCH v8 0/7] Support RAS virtualization in KVM
by Dongjiu Geng
This series patches mainly do below things:
1. Trap RAS ERR* registers Accesses to EL2 from Non-secure EL1,
KVM will will do a minimum simulation, there registers are simulated
to RAZ/WI in KVM.
2. Route synchronous External Abort exceptions from Non-secure EL0
and EL1 to EL2. When exception EL3 routing is enabled by firmware,
system will trap to EL3 firmware instead of EL2 KVM, then firmware
judges whether El2 routing is enabled, if enabled, jump to EL2 KVM,
otherwise jump to EL1 host kernel.
3. Enable APEI ARv8 SEI notification to parse the CPER records for SError
in the ACPI GHES driver, KVM will call handle_guest_sei() to let ACPI
driver to parse the CPER record for SError which happened in the guest
4. Although we can use APEI driver to handle the guest SError, but not all
system support SEI notification, such as kernel-first. So here KVM will
also classify the Error through Exception Syndrome Register and do different
approaches according to Asynchronous Error Type
5. If the guest SError error is not propagated and not consumed, then KVM return
recoverable error status to user-space, user-space will specify the guest ESR
and inject a virtual SError. For other Asynchronous Error Type, KVM directly
injects virtual SError with IMPLEMENTATION DEFINED ESR or KVM is panic if the
error is fatal. In the RAS extension, guest virtual ESR must be set, because
all-zero means 'RAS error: Uncategorized' instead of 'no valid ISS', so set
this ESR to IMPLEMENTATION DEFINED by default if user space does not specify it.
Dongjiu Geng (5):
acpi: apei: Add SEI notification type support for ARMv8
KVM: arm64: Trap RAS error registers and set HCR_EL2's TERR & TEA
arm64: kvm: Introduce KVM_ARM_SET_SERROR_ESR ioctl
arm64: kvm: Set Virtual SError Exception Syndrome for guest
arm64: kvm: handle SError Interrupt by categorization
James Morse (1):
KVM: arm64: Save ESR_EL2 on guest SError
Xie XiuQi (1):
arm64: cpufeature: Detect CPU RAS Extentions
Documentation/virtual/kvm/api.txt | 11 ++++++
arch/arm/include/asm/kvm_host.h | 1 +
arch/arm/kvm/guest.c | 9 +++++
arch/arm64/Kconfig | 16 +++++++++
arch/arm64/include/asm/barrier.h | 1 +
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/include/asm/esr.h | 15 ++++++++
arch/arm64/include/asm/kvm_arm.h | 2 ++
arch/arm64/include/asm/kvm_asm.h | 3 ++
arch/arm64/include/asm/kvm_emulate.h | 17 +++++++++
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/include/asm/sysreg.h | 15 ++++++++
arch/arm64/include/asm/system_misc.h | 1 +
arch/arm64/kernel/cpufeature.c | 13 +++++++
arch/arm64/kernel/process.c | 3 ++
arch/arm64/kvm/guest.c | 14 ++++++++
arch/arm64/kvm/handle_exit.c | 67 +++++++++++++++++++++++++++++++++---
arch/arm64/kvm/hyp/switch.c | 31 +++++++++++++++--
arch/arm64/kvm/inject_fault.c | 13 ++++++-
arch/arm64/kvm/reset.c | 3 ++
arch/arm64/kvm/sys_regs.c | 10 ++++++
arch/arm64/mm/fault.c | 16 +++++++++
drivers/acpi/apei/Kconfig | 15 ++++++++
drivers/acpi/apei/ghes.c | 53 ++++++++++++++++++++++++++++
include/acpi/ghes.h | 1 +
include/uapi/linux/kvm.h | 3 ++
virt/kvm/arm/arm.c | 7 ++++
27 files changed, 336 insertions(+), 9 deletions(-)
--
1.9.1
4 years, 5 months
[PATCH v4 0/9] Support PPTT for ARM64
by Jeremy Linton
ACPI 6.2 adds the Processor Properties Topology Table (PPTT), which is
used to describe the processor and cache topology. Ideally it is
used to extend/override information provided by the hardware, but
right now ARM64 is entirely dependent on firmware provided tables.
This patch parses the table for the cache topology and CPU topology.
New in the v4 we rename the topology cluster_id to physical_id
to match the kernel macro using it, and as its unlikley to actually
map to a cluster on an ACPI system. When we enable ACPI/PPTT for
arm64 we map the physical_id to the PPTT node flagged as the
physical package by the firmware. This results in topologies that
match what the remainder of the system expects.
For example on juno:
[[email protected] topology]# lstopo-no-graphics
Package L#0
L2 L#0 (1024KB)
L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
L2 L#1 (2048KB)
L1d L#4 (32KB) + L1i L#4 (48KB) + Core L#4 + PU L#4 (P#4)
L1d L#5 (32KB) + L1i L#5 (48KB) + Core L#5 + PU L#5 (P#5)
HostBridge L#0
PCIBridge
PCIBridge
PCIBridge
PCI 1095:3132
Block(Disk) L#0 "sda"
PCIBridge
PCI 1002:68f9
GPU L#1 "renderD128"
GPU L#2 "card0"
GPU L#3 "controlD64"
PCIBridge
PCI 11ab:4380
Net L#4 "enp8s0"
Git tree at:
http://linux-arm.org/git?p=linux-jlinton.git
branch: pptt_v4
v3->v4:
Suppress the "Found duplicate cache level/type..." message if the
duplicate cache entry is actually a duplicate node. This allows cases
like L1I and L1D nodes that point at the same L2 node to be accepted
without the warning.
Remove cluster/physical split code. Add a patch to rename cluster_id
so that its clear the topology may not be referring to a cluster.
Add additional ACPICA patch for the PPTT cache properties. This matches
an outstanding ACPICA pull that should be merged in the near future.
Replace a number of (struct*)((u8*)ptr+offset) constructs with ACPI_ADD_PTR
Split out the topology parsing into an additional patch.
Tweak the cpu topology code to terminate on either a level, or a flag.
Add an additional function which retrives the physical package id
for a given cpu.
Various other comments/tweaks.
v2->v3:
Remove valid bit check on leaf nodes. Now simply being a leaf node
is sufficient to verify the processor id against the ACPI
processor ids (gotten from MADT).
Use the acpi processor for the "level 0" Id. This makes the /sys
visible core/thread ids more human readable if the firmware uses
small consecutive values for processor ids.
Added PPTT to the list of injectable ACPI tables.
Fix bug which kept the code from using the processor node as intended
in v2, caused by misuse of git rebase/fixup.
v1->v2:
The parser keys off the acpi_pptt_processor node to determine
unique cache's rather than the acpi_pptt_cache referenced by the
processor node. This allows PPTT tables which "share" cache nodes
across cpu nodes despite not being a shared cache.
Normalize the socket, cluster and thread mapping so that they match
linux's traditional mapping for the physical id, and thread id.
Adding explicit scheduler knowledge of clusters (rather than just
their cache sharing attributes) is a subject for a future patch.
Jeremy Linton (9):
ACPICA: Add additional PPTT flags for cache properties
ACPI/PPTT: Add Processor Properties Topology Table parsing
arm64/acpi: Create arch specific cpu to acpi id helper
ACPI: Enable PPTT support on ARM64
drivers: base: cacheinfo: arm64: Add support for ACPI based firmware
tables
ACPI/PPTT: Add topology parsing code
arm64: Topology, rename cluster_id
arm64: topology: Enable ACPI/PPTT based CPU topology.
ACPI: Add PPTT to injectable table list
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/acpi.h | 4 +
arch/arm64/include/asm/topology.h | 4 +-
arch/arm64/kernel/cacheinfo.c | 23 +-
arch/arm64/kernel/topology.c | 74 ++++-
drivers/acpi/Kconfig | 3 +
drivers/acpi/Makefile | 1 +
drivers/acpi/pptt.c | 570 ++++++++++++++++++++++++++++++++++++++
drivers/acpi/tables.c | 3 +-
drivers/base/cacheinfo.c | 17 +-
include/acpi/actbl1.h | 14 +
include/linux/cacheinfo.h | 11 +-
include/linux/topology.h | 2 +
13 files changed, 697 insertions(+), 30 deletions(-)
create mode 100644 drivers/acpi/pptt.c
--
2.13.5
4 years, 7 months
Re: [Devel] [PATCH v4 2/9] ACPI/PPTT: Add Processor Properties Topology Table parsing
by Jeremy Linton
Hi,
On 11/15/2017 03:27 AM, Xiongfeng Wang wrote:
> Hi Jeremy,
>
> On 2017/11/10 5:03, Jeremy Linton wrote:
>> ACPI 6.2 adds a new table, which describes how processing units
>> are related to each other in tree like fashion. Caches are
>> also sprinkled throughout the tree and describe the properties
>> of the caches in relation to other caches and processing units.
>>
>> Add the code to parse the cache hierarchy and report the total
>> number of levels of cache for a given core using
>> acpi_find_last_cache_level() as well as fill out the individual
>> cores cache information with cache_setup_acpi() once the
>> cpu_cacheinfo structure has been populated by the arch specific
>> code.
>>
>> Further, report peers in the topology using setup_acpi_cpu_topology()
>> to report a unique ID for each processing unit at a given level
>> in the tree. These unique id's can then be used to match related
>> processing units which exist as threads, COD (clusters
>> on die), within a given package, etc.
>>
>> Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com>
>> ---
>> drivers/acpi/pptt.c | 452 ++++++++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 452 insertions(+)
>> create mode 100644 drivers/acpi/pptt.c
>>
>> diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c
>> new file mode 100644
>> index 000000000000..9c9b8b4660e0
>> --- /dev/null
>> +++ b/drivers/acpi/pptt.c
>> @@ -0,0 +1,452 @@
>> +/*
>> + * Copyright (C) 2017, ARM
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * This file implements parsing of Processor Properties Topology Table (PPTT)
>> + * which is optionally used to describe the processor and cache topology.
>> + * Due to the relative pointers used throughout the table, this doesn't
>> + * leverage the existing subtable parsing in the kernel.
>> + *
>> + * The PPTT structure is an inverted tree, with each node potentially
>> + * holding one or two inverted tree data structures describing
>> + * the caches available at that level. Each cache structure optionally
>> + * contains properties describing the cache at that level which can be
>> + * used to override hardware/probed values.
>> + */
>> +#define pr_fmt(fmt) "ACPI PPTT: " fmt
>> +
>> +#include <linux/acpi.h>
>> +#include <linux/cacheinfo.h>
>> +#include <acpi/processor.h>
>> +
>> +/*
>> + * Given the PPTT table, find and verify that the subtable entry
>> + * is located within the table
>> + */
>> +static struct acpi_subtable_header *fetch_pptt_subtable(
>> + struct acpi_table_header *table_hdr, u32 pptt_ref)
>> +{
>> + struct acpi_subtable_header *entry;
>> +
>> + /* there isn't a subtable at reference 0 */
>> + if (pptt_ref < sizeof(struct acpi_subtable_header))
>> + return NULL;
>> +
>> + if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length)
>> + return NULL;
>> +
>> + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, pptt_ref);
>> +
>> + if (pptt_ref + entry->length > table_hdr->length)
>> + return NULL;
>> +
>> + return entry;
>> +}
>> +
>> +static struct acpi_pptt_processor *fetch_pptt_node(
>> + struct acpi_table_header *table_hdr, u32 pptt_ref)
>> +{
>> + return (struct acpi_pptt_processor *)fetch_pptt_subtable(table_hdr,
>> + pptt_ref);
>> +}
>> +
>> +static struct acpi_pptt_cache *fetch_pptt_cache(
>> + struct acpi_table_header *table_hdr, u32 pptt_ref)
>> +{
>> + return (struct acpi_pptt_cache *)fetch_pptt_subtable(table_hdr,
>> + pptt_ref);
>> +}
>> +
>> +static struct acpi_subtable_header *acpi_get_pptt_resource(
>> + struct acpi_table_header *table_hdr,
>> + struct acpi_pptt_processor *node, int resource)
>> +{
>> + u32 *ref;
>> +
>> + if (resource >= node->number_of_priv_resources)
>> + return NULL;
>> +
>> + ref = ACPI_ADD_PTR(u32, node, sizeof(struct acpi_pptt_processor));
>> + ref += resource;
>> +
>> + return fetch_pptt_subtable(table_hdr, *ref);
>> +}
>> +
>> +/*
>> + * Attempt to find a given cache level, while counting the max number
>> + * of cache levels for the cache node.
>> + *
>> + * Given a pptt resource, verify that it is a cache node, then walk
>> + * down each level of caches, counting how many levels are found
>> + * as well as checking the cache type (icache, dcache, unified). If a
>> + * level & type match, then we set found, and continue the search.
>> + * Once the entire cache branch has been walked return its max
>> + * depth.
>> + */
>> +static int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr,
>> + int local_level,
>> + struct acpi_subtable_header *res,
>> + struct acpi_pptt_cache **found,
>> + int level, int type)
>> +{
>> + struct acpi_pptt_cache *cache;
>> +
>> + if (res->type != ACPI_PPTT_TYPE_CACHE)
>> + return 0;
>> +
>> + cache = (struct acpi_pptt_cache *) res;
>> + while (cache) {
>> + local_level++;
>> +
>> + if ((local_level == level) &&
>> + (cache->flags & ACPI_PPTT_CACHE_TYPE_VALID) &&
>> + ((cache->attributes & ACPI_PPTT_MASK_CACHE_TYPE) == type)) {
>> + if ((*found != NULL) && (cache != *found))
>> + pr_err("Found duplicate cache level/type unable to determine uniqueness\n");
>> +
>> + pr_debug("Found cache @ level %d\n", level);
>> + *found = cache;
>> + /*
>> + * continue looking at this node's resource list
>> + * to verify that we don't find a duplicate
>> + * cache node.
>> + */
>> + }
>> + cache = fetch_pptt_cache(table_hdr, cache->next_level_of_cache);
>> + }
>> + return local_level;
>> +}
>> +
>> +/*
>> + * Given a CPU node look for cache levels that exist at this level, and then
>> + * for each cache node, count how many levels exist below (logically above) it.
>> + * If a level and type are specified, and we find that level/type, abort
>> + * processing and return the acpi_pptt_cache structure.
>> + */
>> +static struct acpi_pptt_cache *acpi_find_cache_level(
>> + struct acpi_table_header *table_hdr,
>> + struct acpi_pptt_processor *cpu_node,
>> + int *starting_level, int level, int type)
>> +{
>> + struct acpi_subtable_header *res;
>> + int number_of_levels = *starting_level;
>> + int resource = 0;
>> + struct acpi_pptt_cache *ret = NULL;
>> + int local_level;
>> +
>> + /* walk down from processor node */
>> + while ((res = acpi_get_pptt_resource(table_hdr, cpu_node, resource))) {
>> + resource++;
>> +
>> + local_level = acpi_pptt_walk_cache(table_hdr, *starting_level,
>> + res, &ret, level, type);
>> + /*
>> + * we are looking for the max depth. Since its potentially
>> + * possible for a given node to have resources with differing
>> + * depths verify that the depth we have found is the largest.
>> + */
>> + if (number_of_levels < local_level)
>> + number_of_levels = local_level;
>> + }
>> + if (number_of_levels > *starting_level)
>> + *starting_level = number_of_levels;
>> +
>> + return ret;
>> +}
>> +
>> +/*
>> + * Given a processor node containing a processing unit, walk into it and count
>> + * how many levels exist solely for it, and then walk up each level until we hit
>> + * the root node (ignore the package level because it may be possible to have
>> + * caches that exist across packages). Count the number of cache levels that
>> + * exist at each level on the way up.
>> + */
>> +static int acpi_process_node(struct acpi_table_header *table_hdr,
>> + struct acpi_pptt_processor *cpu_node)
>> +{
>> + int total_levels = 0;
>> +
>> + do {
>> + acpi_find_cache_level(table_hdr, cpu_node, &total_levels, 0, 0);
>> + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent);
>> + } while (cpu_node);
>> +
>> + return total_levels;
>> +}
>> +
>> +/*
>> + * Determine if the *node parameter is a leaf node by iterating the
>> + * PPTT table, looking for nodes which reference it.
>> + * Return 0 if we find a node refrencing the passed node,
>> + * or 1 if we don't.
>> + */
>> +static int acpi_pptt_leaf_node(struct acpi_table_header *table_hdr,
>> + struct acpi_pptt_processor *node)
>> +{
>> + struct acpi_subtable_header *entry;
>> + unsigned long table_end;
>> + u32 node_entry;
>> + struct acpi_pptt_processor *cpu_node;
>> +
>> + table_end = (unsigned long)table_hdr + table_hdr->length;
>> + node_entry = ACPI_PTR_DIFF(node, table_hdr);
>> + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr,
>> + sizeof(struct acpi_table_pptt));
>> +
>> + while ((unsigned long)(entry + 1) < table_end) {
>> + cpu_node = (struct acpi_pptt_processor *)entry;
>> + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) &&
>> + (cpu_node->parent == node_entry))
>> + return 0;
>> + entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry,
>> + entry->length);
>> + }
>> + return 1;
>> +}
>> +
>> +/*
>> + * Find the subtable entry describing the provided processor.
>> + * This is done by iterating the PPTT table looking for processor nodes
>> + * which have an acpi_processor_id that matches the acpi_cpu_id parameter
>> + * passed into the function. If we find a node that matches this criteria
>> + * we verify that its a leaf node in the topology rather than depending
>> + * on the valid flag, which doesn't need to be set for leaf nodes.
>> + */
>> +static struct acpi_pptt_processor *acpi_find_processor_node(
>> + struct acpi_table_header *table_hdr,
>> + u32 acpi_cpu_id)
>> +{
>> + struct acpi_subtable_header *entry;
>> + unsigned long table_end;
>> + struct acpi_pptt_processor *cpu_node;
>> +
>> + table_end = (unsigned long)table_hdr + table_hdr->length;
>> + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr,
>> + sizeof(struct acpi_table_pptt));
>> +
>> + /* find the processor structure associated with this cpuid */
>> + while ((unsigned long)(entry + 1) < table_end) {
>> + cpu_node = (struct acpi_pptt_processor *)entry;
>> +
>> + if (entry->length == 0) {
>> + pr_err("Invalid zero length subtable\n");
>> + break;
>> + }
>> + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) &&
>> + (acpi_cpu_id == cpu_node->acpi_processor_id) &&
>> + acpi_pptt_leaf_node(table_hdr, cpu_node)) {
>> + return (struct acpi_pptt_processor *)entry;
>> + }
>> +
>> + entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry,
>> + entry->length);
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> +static int acpi_find_cache_levels(struct acpi_table_header *table_hdr,
>> + u32 acpi_cpu_id)
>> +{
>> + int number_of_levels = 0;
>> + struct acpi_pptt_processor *cpu;
>> +
>> + cpu = acpi_find_processor_node(table_hdr, acpi_cpu_id);
>> + if (cpu)
>> + number_of_levels = acpi_process_node(table_hdr, cpu);
>> +
>> + return number_of_levels;
>> +}
>> +
>> +/* Convert the linux cache_type to a ACPI PPTT cache type value */
>> +static u8 acpi_cache_type(enum cache_type type)
>> +{
>> + switch (type) {
>> + case CACHE_TYPE_DATA:
>> + pr_debug("Looking for data cache\n");
>> + return ACPI_PPTT_CACHE_TYPE_DATA;
>> + case CACHE_TYPE_INST:
>> + pr_debug("Looking for instruction cache\n");
>> + return ACPI_PPTT_CACHE_TYPE_INSTR;
>> + default:
>> + case CACHE_TYPE_UNIFIED:
>> + pr_debug("Looking for unified cache\n");
>> + /*
>> + * It is important that ACPI_PPTT_CACHE_TYPE_UNIFIED
>> + * contains the bit pattern that will match both
>> + * ACPI unified bit patterns because we use it later
>> + * to match both cases.
>> + */
>> + return ACPI_PPTT_CACHE_TYPE_UNIFIED;
>> + }
>> +}
>> +
>> +/* find the ACPI node describing the cache type/level for the given CPU */
>> +static struct acpi_pptt_cache *acpi_find_cache_node(
>> + struct acpi_table_header *table_hdr, u32 acpi_cpu_id,
>> + enum cache_type type, unsigned int level,
>> + struct acpi_pptt_processor **node)
>> +{
>> + int total_levels = 0;
>> + struct acpi_pptt_cache *found = NULL;
>> + struct acpi_pptt_processor *cpu_node;
>> + u8 acpi_type = acpi_cache_type(type);
>> +
>> + pr_debug("Looking for CPU %d's level %d cache type %d\n",
>> + acpi_cpu_id, level, acpi_type);
>> +
>> + cpu_node = acpi_find_processor_node(table_hdr, acpi_cpu_id);
>> +
>> + while ((cpu_node) && (!found)) {
>> + found = acpi_find_cache_level(table_hdr, cpu_node,
>> + &total_levels, level, acpi_type);
>> + *node = cpu_node;
>> + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent);
>> + }
>> +
>> + return found;
>> +}
>> +
>> +/*
>> + * The ACPI spec implies that the fields in the cache structures are used to
>> + * extend and correct the information probed from the hardware. In the case
>> + * of arm64 the CCSIDR probing has been removed because it might be incorrect.
>> + */
>> +static void update_cache_properties(struct cacheinfo *this_leaf,
>> + struct acpi_pptt_cache *found_cache,
>> + struct acpi_pptt_processor *cpu_node)
>> +{
>> + if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID)
>> + this_leaf->size = found_cache->size;
>> + if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID)
>> + this_leaf->coherency_line_size = found_cache->line_size;
>> + if (found_cache->flags & ACPI_PPTT_NUMBER_OF_SETS_VALID)
>> + this_leaf->number_of_sets = found_cache->number_of_sets;
>> + if (found_cache->flags & ACPI_PPTT_ASSOCIATIVITY_VALID)
>> + this_leaf->ways_of_associativity = found_cache->associativity;
>> + if (found_cache->flags & ACPI_PPTT_WRITE_POLICY_VALID)
>> + switch (found_cache->attributes & ACPI_PPTT_MASK_WRITE_POLICY) {
>> + case ACPI_PPTT_CACHE_POLICY_WT:
>> + this_leaf->attributes = CACHE_WRITE_THROUGH;
>> + break;
>> + case ACPI_PPTT_CACHE_POLICY_WB:
>> + this_leaf->attributes = CACHE_WRITE_BACK;
>> + break;
>> + }
>> + if (found_cache->flags & ACPI_PPTT_ALLOCATION_TYPE_VALID)
>> + switch (found_cache->attributes & ACPI_PPTT_MASK_ALLOCATION_TYPE) {
>> + case ACPI_PPTT_CACHE_READ_ALLOCATE:
>> + this_leaf->attributes |= CACHE_READ_ALLOCATE;
>> + break;
>> + case ACPI_PPTT_CACHE_WRITE_ALLOCATE:
>> + this_leaf->attributes |= CACHE_WRITE_ALLOCATE;
>> + break;
>> + case ACPI_PPTT_CACHE_RW_ALLOCATE:
>> + case ACPI_PPTT_CACHE_RW_ALLOCATE_ALT:
>> + this_leaf->attributes |=
>> + CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE;
>> + break;
>> + }
>> +}
>> +
>
First, thanks for testing this!
> I test this patch on our platform, and the result is that 'type' property of L3Cache
> is not displayed.
>
> So I add some print to debug, and found out that ARM64 __populate_cache_leaves()
> set this_cpu_ci->info_list[L3Cache_level].type to 0, bacause we can't get the type of
> L3Cache from CLIDR.
>
> Then cache_setup_acpi_cpu() try to find L3Cache from PPTT. Because L3Cache type read from
> CLIDR is 0, so branch in acpi_cache_type falls into default: ACPI_PPTT_CACHE_TYPE_UNIFIED.
> So we can find L3Cache in PPTT, then use update_cache_properties() to update L3Cache property.
> But update_cache_properties() doesn't update the cache type, so this_cpu_ci->info_list[L3Cache_level].type
> is still 0, cache_default_attrs_is_visible() returns 0, and 'type' property of L3Cache won't be displayed in sysfs.
Oh, right! The other implication is that you can't add caches which
aren't unified if they aren't detected by the cache description registers.
>
> Can we set this_cpu_ci->info_list[level].type to CACHE_TYPE_UNIFIED in __populate_cache_leaves() when level >= 3 ?
> Or can we update cache type property in update_cache_properties() ?
Sure, I think maybe updating it here in update_cache_properties is a
better plan if we can assure that enough of the fields are valid that we
aren't just displaying a zero size cache in sysfs..
>
>
> Thanks,
> Xiongfeng Wang
>
>
>> +/*
>> + * Update the kernel cache information for each level of cache
>> + * associated with the given acpi cpu.
>> + */
>> +static void cache_setup_acpi_cpu(struct acpi_table_header *table,
>> + unsigned int cpu)
>> +{
>> + struct acpi_pptt_cache *found_cache;
>> + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
>> + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
>> + struct cacheinfo *this_leaf;
>> + unsigned int index = 0;
>> + struct acpi_pptt_processor *cpu_node = NULL;
>> +
>> + while (index < get_cpu_cacheinfo(cpu)->num_leaves) {
>> + this_leaf = this_cpu_ci->info_list + index;
>> + found_cache = acpi_find_cache_node(table, acpi_cpu_id,
>> + this_leaf->type,
>> + this_leaf->level,
>> + &cpu_node);
>> + pr_debug("found = %p %p\n", found_cache, cpu_node);
>> + if (found_cache)
>> + update_cache_properties(this_leaf,
>> + found_cache,
>> + cpu_node);
>> +
>> + index++;
>> + }
>> +}
>> +
>> +/**
>> + * acpi_find_last_cache_level() - Determines the number of cache levels for a PE
>> + * @cpu: Kernel logical cpu number
>> + *
>> + * Given a logical cpu number, returns the number of levels of cache represented
>> + * in the PPTT. Errors caused by lack of a PPTT table, or otherwise, return 0
>> + * indicating we didn't find any cache levels.
>> + *
>> + * Return: Cache levels visible to this core.
>> + */
>> +int acpi_find_last_cache_level(unsigned int cpu)
>> +{
>> + u32 acpi_cpu_id;
>> + struct acpi_table_header *table;
>> + int number_of_levels = 0;
>> + acpi_status status;
>> +
>> + pr_debug("Cache Setup find last level cpu=%d\n", cpu);
>> +
>> + acpi_cpu_id = get_acpi_id_for_cpu(cpu);
>> + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table);
>> + if (ACPI_FAILURE(status)) {
>> + pr_err_once("No PPTT table found, cache topology may be inaccurate\n");
>> + } else {
>> + number_of_levels = acpi_find_cache_levels(table, acpi_cpu_id);
>> + acpi_put_table(table);
>> + }
>> + pr_debug("Cache Setup find last level level=%d\n", number_of_levels);
>> +
>> + return number_of_levels;
>> +}
>> +
>> +/**
>> + * cache_setup_acpi() - Override CPU cache topology with data from the PPTT
>> + * @cpu: Kernel logical cpu number
>> + *
>> + * Updates the global cache info provided by cpu_get_cacheinfo()
>> + * when there are valid properties in the acpi_pptt_cache nodes. A
>> + * successful parse may not result in any updates if none of the
>> + * cache levels have any valid flags set. Futher, a unique value is
>> + * associated with each known CPU cache entry. This unique value
>> + * can be used to determine whether caches are shared between cpus.
>> + *
>> + * Return: -ENOENT on failure to find table, or 0 on success
>> + */
>> +int cache_setup_acpi(unsigned int cpu)
>> +{
>> + struct acpi_table_header *table;
>> + acpi_status status;
>> +
>> + pr_debug("Cache Setup ACPI cpu %d\n", cpu);
>> +
>> + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table);
>> + if (ACPI_FAILURE(status)) {
>> + pr_err_once("No PPTT table found, cache topology may be inaccurate\n");
>> + return -ENOENT;
>> + }
>> +
>> + cache_setup_acpi_cpu(table, cpu);
>> + acpi_put_table(table);
>> +
>> + return status;
>> +}
>>
>
4 years, 7 months
[pm:bleeding-edge 5/6] arch/x86/kernel/cpu/proc.c:83: undefined reference to `aperfmperf_get_khz'
by kbuild test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git bleeding-edge
head: f379d4b265627033aa2f4d68464df7ae3a6a11c9
commit: a1823cba722b8f403f6ad83ec79b17773817fb27 [5/6] x86 / CPU: Always show current CPU frequency in /proc/cpuinfo
config: i386-randconfig-s0-201746 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout a1823cba722b8f403f6ad83ec79b17773817fb27
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
arch/x86/kernel/cpu/proc.o: In function `show_cpuinfo':
>> arch/x86/kernel/cpu/proc.c:83: undefined reference to `aperfmperf_get_khz'
vim +83 arch/x86/kernel/cpu/proc.c
56
57 static int show_cpuinfo(struct seq_file *m, void *v)
58 {
59 struct cpuinfo_x86 *c = v;
60 unsigned int cpu;
61 int i;
62
63 cpu = c->cpu_index;
64 seq_printf(m, "processor\t: %u\n"
65 "vendor_id\t: %s\n"
66 "cpu family\t: %d\n"
67 "model\t\t: %u\n"
68 "model name\t: %s\n",
69 cpu,
70 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
71 c->x86,
72 c->x86_model,
73 c->x86_model_id[0] ? c->x86_model_id : "unknown");
74
75 if (c->x86_mask || c->cpuid_level >= 0)
76 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
77 else
78 seq_puts(m, "stepping\t: unknown\n");
79 if (c->microcode)
80 seq_printf(m, "microcode\t: 0x%x\n", c->microcode);
81
82 if (cpu_has(c, X86_FEATURE_TSC)) {
> 83 unsigned int freq = aperfmperf_get_khz(cpu);
84
85 if (!freq)
86 freq = cpufreq_quick_get(cpu);
87 if (!freq)
88 freq = cpu_khz;
89 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
90 freq / 1000, (freq % 1000));
91 }
92
93 /* Cache size */
94 if (c->x86_cache_size >= 0)
95 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
96
97 show_cpuinfo_core(m, c, cpu);
98 show_cpuinfo_misc(m, c);
99
100 seq_puts(m, "flags\t\t:");
101 for (i = 0; i < 32*NCAPINTS; i++)
102 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
103 seq_printf(m, " %s", x86_cap_flags[i]);
104
105 seq_puts(m, "\nbugs\t\t:");
106 for (i = 0; i < 32*NBUGINTS; i++) {
107 unsigned int bug_bit = 32*NCAPINTS + i;
108
109 if (cpu_has_bug(c, bug_bit) && x86_bug_flags[i])
110 seq_printf(m, " %s", x86_bug_flags[i]);
111 }
112
113 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
114 c->loops_per_jiffy/(500000/HZ),
115 (c->loops_per_jiffy/(5000/HZ)) % 100);
116
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
4 years, 7 months
ACPICA version 20171110 released
by Moore, Robert
10 November 2017. Summary of changes for version 20171110:
This release is available at https://acpica.org/downloads
1) ACPICA kernel-resident subsystem:
This release implements full support for ACPI 6.2A:
NFIT - Added a new subtable, "Platform Capabilities Structure"
No other changes to ACPICA were required, since ACPI 6.2A is primarily an errata release of the specification.
Other ACPI table changes:
IORT: Added the SMMUv3 Device ID mapping index. Hanjun Guo
PPTT: Added cache attribute flag definitions to actbl1.h. Jeremy Linton
Utilities: Modified the string/integer conversion functions to use internal 64-bit divide support instead of a native divide. On 32-bit platforms, a 64-bit divide typically requires a library function which may not be present in the build (kernel or otherwise).
Implemented a targeted error message for timeouts returned from the Embedded Controller device driver. This is seen frequently enough to special-case an AE_TIME returned from an EC operation region access:
"Timeout from EC hardware or EC device driver"
Changed the "ACPI Exception" message prefix to "ACPI Error" so that all runtime error messages have the identical prefix.
2) iASL Compiler/Disassembler and Tools:
AcpiXtract: Fixed a problem with table header detection within the acpidump file. Processing a table could be ended early if a 0x40 (@) appears in the original binary table, resulting in the @ symbol appearing in the decoded ASCII field at the end of the acpidump text line. The symbol caused acpixtract to incorrectly think it had reached the end of the current table and the beginning of a new table.
AcpiXtract: Added an option (-f) to ignore some errors during table extraction. This initial implementation ignores non-ASCII and non-printable characters found in the acpidump text file.
TestSuite(ASLTS)/AcpiExec: Fixed and restored the memory usage statistics for ASLTS. This feature is used to track memory allocations from different memory caches within the ACPICA code. At the end of an ASLTS run, these memory statistics are recorded and stored in a log file.
Debugger (user-space version): Implemented a simple "Background" command. Creates a new thread to execute a control method in the background, while control returns to the debugger prompt to allow additional commands.
Syntax: Background <Namepath> [Arguments]
4 years, 7 months
[pm:bleeding-edge 133/152] drivers/acpi/pmic/intel_pmic_crc.c:195:4: warning: passing argument 4 of 'intel_pmic_install_opregion_handler' discards 'const' qualifier from pointer target type
by kbuild test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git bleeding-edge
head: ae05952223bd043c0f75cf13f5397e57809edb23
commit: 3b9db22203b8026b0c2e5eb6823e267a2ce71179 [133/152] ACPI / PMIC: make intel_pmic_opregion_data structures const
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
git checkout 3b9db22203b8026b0c2e5eb6823e267a2ce71179
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
drivers/acpi/pmic/intel_pmic_crc.c: In function 'intel_crc_pmic_opregion_probe':
>> drivers/acpi/pmic/intel_pmic_crc.c:195:4: warning: passing argument 4 of 'intel_pmic_install_opregion_handler' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
&intel_crc_pmic_opregion_data);
^
In file included from drivers/acpi/pmic/intel_pmic_crc.c:21:0:
drivers/acpi/pmic/intel_pmic.h:23:5: note: expected 'struct intel_pmic_opregion_data *' but argument is of type 'const struct intel_pmic_opregion_data *'
int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle, struct regmap *regmap, struct intel_pmic_opregion_data *d);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--
drivers/acpi/pmic/intel_pmic_bxtwc.c: In function 'intel_bxtwc_pmic_opregion_probe':
>> drivers/acpi/pmic/intel_pmic_bxtwc.c:400:4: warning: passing argument 4 of 'intel_pmic_install_opregion_handler' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
&intel_bxtwc_pmic_opregion_data);
^
In file included from drivers/acpi/pmic/intel_pmic_bxtwc.c:21:0:
drivers/acpi/pmic/intel_pmic.h:23:5: note: expected 'struct intel_pmic_opregion_data *' but argument is of type 'const struct intel_pmic_opregion_data *'
int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle, struct regmap *regmap, struct intel_pmic_opregion_data *d);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--
drivers/acpi/pmic/intel_pmic_chtwc.c: In function 'intel_cht_wc_pmic_opregion_probe':
>> drivers/acpi/pmic/intel_pmic_chtwc.c:260:4: warning: passing argument 4 of 'intel_pmic_install_opregion_handler' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
&intel_cht_wc_pmic_opregion_data);
^
In file included from drivers/acpi/pmic/intel_pmic_chtwc.c:23:0:
drivers/acpi/pmic/intel_pmic.h:23:5: note: expected 'struct intel_pmic_opregion_data *' but argument is of type 'const struct intel_pmic_opregion_data *'
int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle, struct regmap *regmap, struct intel_pmic_opregion_data *d);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +195 drivers/acpi/pmic/intel_pmic_crc.c
b1eea857 Aaron Lu 2014-11-24 189
b1eea857 Aaron Lu 2014-11-24 190 static int intel_crc_pmic_opregion_probe(struct platform_device *pdev)
b1eea857 Aaron Lu 2014-11-24 191 {
b1eea857 Aaron Lu 2014-11-24 192 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
b1eea857 Aaron Lu 2014-11-24 193 return intel_pmic_install_opregion_handler(&pdev->dev,
b1eea857 Aaron Lu 2014-11-24 194 ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
b1eea857 Aaron Lu 2014-11-24 @195 &intel_crc_pmic_opregion_data);
b1eea857 Aaron Lu 2014-11-24 196 }
b1eea857 Aaron Lu 2014-11-24 197
:::::: The code at line 195 was first introduced by commit
:::::: b1eea857d8c70dc3789cc2231e3c0a273a67ba06 ACPI / PMIC: support PMIC operation region for CrystalCove
:::::: TO: Aaron Lu <aaron.lu(a)intel.com>
:::::: CC: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
4 years, 7 months
[pm:bleeding-edge 133/152] drivers/acpi/pmic/intel_pmic_xpower.c:266:6: warning: passing argument 4 of 'intel_pmic_install_opregion_handler' discards 'const' qualifier from pointer target type
by kbuild test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git bleeding-edge
head: ae05952223bd043c0f75cf13f5397e57809edb23
commit: 3b9db22203b8026b0c2e5eb6823e267a2ce71179 [133/152] ACPI / PMIC: make intel_pmic_opregion_data structures const
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 6.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 3b9db22203b8026b0c2e5eb6823e267a2ce71179
# save the attached .config to linux build tree
make.cross ARCH=ia64
All warnings (new ones prefixed by >>):
drivers/acpi/pmic/intel_pmic_xpower.c: In function 'intel_xpower_pmic_opregion_probe':
>> drivers/acpi/pmic/intel_pmic_xpower.c:266:6: warning: passing argument 4 of 'intel_pmic_install_opregion_handler' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
&intel_xpower_pmic_opregion_data);
^
In file included from drivers/acpi/pmic/intel_pmic_xpower.c:21:0:
drivers/acpi/pmic/intel_pmic.h:23:5: note: expected 'struct intel_pmic_opregion_data *' but argument is of type 'const struct intel_pmic_opregion_data *'
int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle, struct regmap *regmap, struct intel_pmic_opregion_data *d);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +266 drivers/acpi/pmic/intel_pmic_xpower.c
d8139f631 Aaron Lu 2014-11-24 250
d8139f631 Aaron Lu 2014-11-24 251 static int intel_xpower_pmic_opregion_probe(struct platform_device *pdev)
d8139f631 Aaron Lu 2014-11-24 252 {
491cb357d Aaron Lu 2014-11-24 253 struct device *parent = pdev->dev.parent;
491cb357d Aaron Lu 2014-11-24 254 struct axp20x_dev *axp20x = dev_get_drvdata(parent);
491cb357d Aaron Lu 2014-11-24 255 acpi_status status;
491cb357d Aaron Lu 2014-11-24 256 int result;
491cb357d Aaron Lu 2014-11-24 257
491cb357d Aaron Lu 2014-11-24 258 status = acpi_install_address_space_handler(ACPI_HANDLE(parent),
491cb357d Aaron Lu 2014-11-24 259 ACPI_ADR_SPACE_GPIO, intel_xpower_pmic_gpio_handler,
491cb357d Aaron Lu 2014-11-24 260 NULL, NULL);
491cb357d Aaron Lu 2014-11-24 261 if (ACPI_FAILURE(status))
491cb357d Aaron Lu 2014-11-24 262 return -ENODEV;
491cb357d Aaron Lu 2014-11-24 263
491cb357d Aaron Lu 2014-11-24 264 result = intel_pmic_install_opregion_handler(&pdev->dev,
491cb357d Aaron Lu 2014-11-24 265 ACPI_HANDLE(parent), axp20x->regmap,
d8139f631 Aaron Lu 2014-11-24 @266 &intel_xpower_pmic_opregion_data);
491cb357d Aaron Lu 2014-11-24 267 if (result)
491cb357d Aaron Lu 2014-11-24 268 acpi_remove_address_space_handler(ACPI_HANDLE(parent),
491cb357d Aaron Lu 2014-11-24 269 ACPI_ADR_SPACE_GPIO,
491cb357d Aaron Lu 2014-11-24 270 intel_xpower_pmic_gpio_handler);
491cb357d Aaron Lu 2014-11-24 271
491cb357d Aaron Lu 2014-11-24 272 return result;
d8139f631 Aaron Lu 2014-11-24 273 }
d8139f631 Aaron Lu 2014-11-24 274
:::::: The code at line 266 was first introduced by commit
:::::: d8139f6311129b4fdc370cbfc03424afea83693b ACPI / PMIC: support PMIC operation region for XPower AXP288
:::::: TO: Aaron Lu <aaron.lu(a)intel.com>
:::::: CC: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
4 years, 7 months
[PATCH v9 0/4] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)
by Shameer Kolothum
On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC
deviates from the standard implementation and this breaks PCIe MSI
functionality when SMMU is enabled.
The HiSilicon erratum 161010801 describes this limitation of certain
HiSilicon platforms to support the SMMU mappings for MSI transactions.
On these platforms GICv3 ITS translator is presented with the deviceID
by extending the MSI payload data to 64 bits to include the deviceID.
Hence, the PCIe controller on this platforms has to differentiate the MSI
payload against other DMA payload and has to modify the MSI payload.
This basically makes it difficult for this platforms to have a SMMU
translation for MSI.
This patch implements an ACPI and DT based quirk to reserve the hw msi
regions in the smmu-v3 driver which means these address regions will
not be translated and will be excluded from iova allocations.
To implement this quirk, the following changes are incorporated:
1. Added a generic helper function to IORT code to retrieve the
associated ITS base address from a device IORT node.
2. Added a generic helper function to of iommu code to retrieve the
associated msi controller base address from for a PCI RC
msi-mapping and also platform device msi-parent.
3. Blacklisted HiSilicon PCIe controllers on DT based hip06/hip07
platforms when SMMUv3 is enabled as there is no DT based solution
for this as of now.
Changelog:
v8 --> v9
-Thanks to Marc, fixed IORT helper function to reserve the ITS
translater region only.
-Removed the DT support for MSI reservation and blacklisted
HiSilicon PCIe controllers on DT based systems when SMMUv3 is
enabled.
v7 --> v8
Addressed comments from Rob and Lorenzo:
-Modified to use DT compatible string for errata.
-Changed logic to retrieve the msi-parent for DT case.
v6 --> v7
Addressed request from Will to add DT support for the erratum:
- added bt binding
- add of_iommu_msi_get_resv_regions()
New arm64 silicon errata entry
Rename iort_iommu_{its->msi}_get_resv_regions
v5 --> v6
Addressed comments from Robin and Lorenzo:
-No change to patch#1 .
-Reverted v5 patch#2 as this might break the platforms where this quirk
is not applicable. Provided a generic function in iommu code and added
back the quirk implementation in SMMU v3 driver(patch#3)
v4 --> v5
Addressed comments from Robin and Lorenzo:
-Added a comment to make it clear that, for now, only straightforward
HW topologies are handled while reserving ITS regions(patch #1).
v3 --> v4
Rebased on 4.13-rc1.
Addressed comments from Robin, Will and Lorenzo:
-As suggested by Robin, moved the ITS msi reservation into
iommu_dma_get_resv_regions().
-Added its_count != resv region failure case(patch #1).
v2 --> v3
Addressed comments from Lorenzo and Robin:
-Removed dev_is_pci() check in smmuV3 driver.
-Don't treat device not having an ITS mapping as an error in
iort helper function.
v1 --> v2
-patch 2/2: Invoke iort helper fn based on fwnode type(acpi).
RFCv2 -->PATCH
-Incorporated Lorenzo's review comments.
RFC v1 --> RFC v2
Based on Robin's review comments,
-Removed the generic erratum framework.
-Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table.
Shameer Kolothum (4):
ACPI/IORT: Add msi address regions reservation helper
iommu/dma: Add a helper function to reserve HW MSI address regions for
IOMMU drivers
iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801
PCI: hisi: blacklist hip06/hip07 controllers behind SMMUv3
drivers/acpi/arm64/iort.c | 97 ++++++++++++++++++++++++++++++++++++++--
drivers/iommu/arm-smmu-v3.c | 27 ++++++++---
drivers/iommu/dma-iommu.c | 20 +++++++++
drivers/irqchip/irq-gic-v3-its.c | 3 +-
drivers/pci/dwc/pcie-hisi.c | 12 +++++
include/linux/acpi_iort.h | 7 ++-
include/linux/dma-iommu.h | 7 +++
7 files changed, 163 insertions(+), 10 deletions(-)
--
1.9.1
4 years, 7 months
[pm:bleeding-edge 80/99] drivers//acpi/sleep.c:95:5: error: redefinition of 'acpi_target_system_state'
by kbuild test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git bleeding-edge
head: 699d53e8c1a7eca5ef152eafee1692c77f2818c0
commit: 8d7a4756fef978edeb7834742f755b526c850fdb [80/99] ACPI / PM: Blacklist Low Power S0 Idle _DSM for Dell XPS13 9360
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 6.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 8d7a4756fef978edeb7834742f755b526c850fdb
# save the attached .config to linux build tree
make.cross ARCH=ia64
All errors (new ones prefixed by >>):
>> drivers//acpi/sleep.c:95:5: error: redefinition of 'acpi_target_system_state'
u32 acpi_target_system_state(void)
^~~~~~~~~~~~~~~~~~~~~~~~
In file included from include/linux/acpi.h:44:0,
from drivers//acpi/sleep.c:20:
include/acpi/acpi_bus.h:661:19: note: previous definition of 'acpi_target_system_state' was here
static inline u32 acpi_target_system_state(void) { return ACPI_STATE_S0; }
^~~~~~~~~~~~~~~~~~~~~~~~
drivers//acpi/sleep.c:495:13: warning: 'acpi_pm_end' defined but not used [-Wunused-function]
static void acpi_pm_end(void)
^~~~~~~~~~~
drivers//acpi/sleep.c:485:13: warning: 'acpi_pm_start' defined but not used [-Wunused-function]
static void acpi_pm_start(u32 acpi_state)
^~~~~~~~~~~~~
drivers//acpi/sleep.c:441:13: warning: 'acpi_pm_finish' defined but not used [-Wunused-function]
static void acpi_pm_finish(void)
^~~~~~~~~~~~~~
drivers//acpi/sleep.c:418:12: warning: 'acpi_pm_prepare' defined but not used [-Wunused-function]
static int acpi_pm_prepare(void)
^~~~~~~~~~~~~~~
vim +/acpi_target_system_state +95 drivers//acpi/sleep.c
a6ae7594b Rafael J. Wysocki 2012-11-02 94
a6ae7594b Rafael J. Wysocki 2012-11-02 @95 u32 acpi_target_system_state(void)
a6ae7594b Rafael J. Wysocki 2012-11-02 96 {
a6ae7594b Rafael J. Wysocki 2012-11-02 97 return acpi_target_sleep_state;
a6ae7594b Rafael J. Wysocki 2012-11-02 98 }
fad16dd9c Rafael J. Wysocki 2014-05-08 99 EXPORT_SYMBOL_GPL(acpi_target_system_state);
a6ae7594b Rafael J. Wysocki 2012-11-02 100
:::::: The code at line 95 was first introduced by commit
:::::: a6ae7594b1b157e0e7976ed105a7be27d69a5361 ACPI / PM: Move device PM functions related to sleep states
:::::: TO: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com>
:::::: CC: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com>
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0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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